As is known and shown in FIG. 1, a ferroelectric cell 1 is composed of a MOS transistor 2 and a capacitor 3 having, as a dielectric, a ferroelectric material, for example PZT (PbZr.sub.1-x Ti.sub.x O.sub.3, perovskite) or SBT (SrBi.sub.2 Ta.sub.2 O.sub.9, layered perovskite). In detail, in the ferroelectric cell 1, the NMOS-type transistor 2 has a source terminal 4 connected to a bit line BL, a gate electrode 5 connected to a word line WL and a drain terminal 6 connected to a first plate 7 of the capacitor 3. A second plate 8 of the capacitor 3 is connected to a plate line PL.
The cell is capable of storing binary information thanks to the hysteresis characteristics of the ferroelectric material which is sandwiched between the plates 7 and 8 and which, when there are no applied voltages, can assume two bias states depending on the sign of previously-applied voltage across the capacitor 3 terminals.
All currently-known ferroelectric cells can be classified into two families: strapped cells and stacked cells.
In strapped cells, an embodiment of which is shown in FIG. 2, the capacitor 3 is constructed above a field oxide region 10 that delimits an active area 11 of the substrate 12 in which the conductive regions (source 13 and drain 14) of the transistor 2 are formed. In detail, the first plate 7 of the capacitor 3 is here placed on top and is made of a square- or rectangular-shaped region of conductive material (for example, platinum), connected to the drain region 14 of the transistor 2 through a metallic connection line 16; the second plate 8 of the capacitor 3 is here placed underneath and is made by a band of conductive material (for example, platinum again) which runs perpendicular to the drawing plane and forms a plate line PL, connected to other capacitors of adjacent cells; a dielectric region 17, of ferroelectric material, is sandwiched between the first plate 7 and the second plate 8. The gate electrode 5 of the transistor 2 is made of a band of polycrystalline silicon which runs perpendicular to the drawing plane and forms a word line WL.
In stacked cells, an embodiment of which can be seen in FIG. 3, the capacitor 3 is constructed above the active area 11, directly above the drain region 14 of the transistor 2. In this case, the first plate 7 of the capacitor 3 is placed underneath and is made by a square- or rectangular-shaped region of conductive material (for example, platinum) connected to the drain region 14 through a contact 23 formed in an opening of a protective layer 24 (for example BPSG) and the second plate 8, of conductive material, is placed above and is connected to a metalization band 25 defining the plate line PL.
A titanium/titanium nitride region 26 runs below the first plate 7 to help the adhesion of the first plate 7 of the capacitor 3 on the protective layer 24.
The architecture of a array 28 of ferroelectric stacked or strapped cells 1 is shown in FIG. 4. It will be noted that the ferroelectric cells 1 are placed on rows and columns and are coupled so that the cell pairs 27 are placed parallel to bit lines BL; the transistors 2 of each cell pair 27 have common source regions, connected to the same bit line BL; and the capacitors 3 belonging to the cell pairs 27 adjacent in a parallel direction to the bit lines BL are connected to adjacent plate line pairs PL.
Ferroelectric stacked cells 1 are currently preferred, since they are the only ones capable of meeting the scalability requirements of new CMOS technologies. In stacked cells, the layout rules on the capacitor 3 design are crucial for the optimization of the cell.